1. Field of the Invention
The present invention generally relates to a proximity IC card (hereinafter sometimes abbreviated to xe2x80x9cPICCxe2x80x9d) and, more particularly, to a carrier synchronization type modulator for receiving a phase-shift-keying (PSK) (modulated) signal sent from a PICC in a PICC reader/writer (hereinafter abbreviated as PICC-R/W) for writing data to and reading data from the PICC.
2. Description of the Related Art
PICC standards are described in ISO/IEC (International Organization for Standardization/International Electrotechnical Commission) 14443. Hereinafter, in relation to the present invention, a brief description is given about part of ISO/IEC 14443, which relates to a type-B communication interface for a PICC and which describes the properties and characteristics of a field that provides power transmission and bidirectional communication between a PICC and a proximity coupling device (hereunder abbreviated to PCD), such as the PICC-R/W.
(1) Power Transmission from PCD to PICC
To supply effective power to the PICC in a radio frequency (RF) operating field, a carrier (having a carrier frequency of fc=13.56 MHz) is transmitted from the PCD to the PICC, whereupon the received carrier is rectified to thereby generate electric power needed for an operation of an internal circuit.
(2) Communication from PCD to PICC
The PCD transmits data to the PICC by amplitude-shift-keying (ASK) modulating the amplitude of the carrier with a modulation index of 10% at a data bit rate of 106 Kbps (=f2/128).
(3) Communication from PICC to PCD
The PICC transmits data to the PCD by performing load modulation of a load for reception of the carrier at a frequency fs (=fc/16), which is ({fraction (1/16)}) the carrier frequency, to thereby generate a subcarrier (whose frequency fs=847 kHz), and by then binary-phase-shift-keying (BPSK) modulating the phase of the subcarrier at a data bit rate of 106 Kbps (=fc/128).
FIG. 1 schematically shows an example of a PICC.
In the case of the example of FIG. 1, two chips respectively constituting a central processing unit (CPU) portion 11 and an RF portion 12 are incorporated into a card body 10. Further, an antenna (AT) 13, wound like a coil, is disposed along the periphery of the card body 10. The CPU portion 11 is constituted by what is called a one-chip computer and includes a CPU, memories such as a ROM, a RAM, and an EEPROM, and an input/output (I/O) interface.
FIG. 2 shows an example of the communication interface between a PCD and a PICC.
In the case of the communication from the PCD to the PICC, which has been described in the foregoing section (2), a modulation portion (MOD) 20 of the PCD performs ASK modulation of the amplitude of a carrier (having the carrier frequency of fc=13.56 MHz) with a modulation index of 10%. Then, a resultant signal is transmitted from the PCD to the PICC through output amplifiers 22 and 23 and an antenna 24.
In contrast, in the case of the communication from the PICC to the PCD, which has been described in the foregoing section (3), a load 26 for reception of an RF signal is varied under the control of a modulation portion (MOD) 28 of the RF portion 12 of the PICC shown in FIG. 1. Then, a BPSK modulation for providing binary phase information (representing 0 or 180 degrees) is performed on a subcarrier (whose frequency f8 =847 KHz) generated by a load modulation (resulting in an amplitude modulation (hereunder referred to as an AM modulation)).
The modulated signal is transmitted to the PCD through an antenna 25 (corresponding to the antenna 13 of FIG. 1). Actually, a detection portion (DET) 21 of the PCD detects the carrier that is outputted by the PCD itself and that undergoes the load modulation (including the BPSK modulation) performed by the PICC, as illustrated in FIG. 2.
FIG. 3 shows an example of a conventional demodulator.
A demodulator 30 is placed at the rear stage of the detection portion 21 of FIG. 2. A PSK-modulated carrier signal is shaped into (whose frequency fs=847 KHz) the digital form (namely, a binary signal) in the detection portion 21 and inputted to the demodulator 30. In the demodulator 30, a frequency doubler 31 of a first stage thereof first doubles the frequency of the received signal so as to reproduce a received subcarrier.
Subsequently, a phase lock loop (PLL) circuit consisting of a phase comparator 32, a low-pass filter (LPF) 33, and a voltage-controlled oscillator (VCO) 34 synchronizes a signal having a period being double the period of a subcarrier, which is produced in the demodulator, with the frequency-doubled signal. Then, the frequency of the former signal is divided by 2 by a divide-by-2 frequency divider 35. Consequently, a demodulation clock phase-synchronized with the received subcarrier is generated.
Further, the BPSK-modulated data signal (having a data bit rate of 106 kbps) representing data, whose 1 bit width corresponds to 8 periods of the subcarrier, is demodulated by sampling the received signals at a leading or trailing edge of the subcarrier signal produced in the demodulator.
FIGS. 4A and 4B illustrate an example of a demodulation operation performed by the sampling of the received signals.
FIG. 4A illustrates such a demodulation operation in the case of normal reception of the BPSK-modulated signal. In this case, 8 subcarriers constituting each bit width of the received PSK signal are sampled at a correct logic level. In contrast, FIG. 4B illustrates such a demodulation operation in the case that external noise affects the BPSK-modulated signal. In this case, the level of the received PSK signal varies owing to the noise, so that the received signal (namely, an output of the comparator), which is erroneously shaped in waveform, is sampled. In the case of this example, unnecessary waveform distortion occurs at a data bit having a logical level xe2x80x9c0xe2x80x9d. This results in erroneous reception of the signal. Consequently, a malfunction of the demodulator 30 occurs.
Thus, the conventional demodulator has drawbacks in that waveform distortion is liable to occur in a demodulation signal when it is affected by a spatial noise, and that the demodulator has low noise immunity. Further, as is apparent from the constitution of the conventional demodulator of FIG. 3, the conventional demodulator has drawbacks in that when a phase delay is introduced in the received PSK signal, the demodulator sometimes fails as a result of the follow-up time of the PLL in demodulating the received PSK signal by utilizing an output of the VCO and that thus, an erroneous code is outputted. This phase delay is regularly caused therein. Thus, a phase compensation circuit is required to compensate for the phase delay by circuit means. Consequently, the conventional demodulator has drawbacks in that the demodulator does not meet demands for reductions in the cost and the size thereof.
In view of the aforementioned drawbacks of the conventional demodulator, the present invention is accomplished by paying attention to the fact that the received subcarrier signal is synchronized with the carrier signal outputted by the PCD in the case of the demodulator for a PSK signal in the PICC.
Accordingly, an object of the present invention is to provide a carrier synchronization type demodulator for a PSK signal, which performs sampling by using a signal synchronized with an own carrier signal without using the conventional PLL circuit, and by then detecting a sampling start point and performing a majority decision on a result of the sampling so as to ensure more stable demodulation.
Further, an object of the present invention is to provide a carrier synchronization type demodulator for a PSK signal, which is enabled to stably receive continuous data arranged at indefinite data intervals by suitably performing an operation of detecting the sampling start point.
Furthermore, an object of the present invention is to provide a carrier synchronization type demodulator, which meets the demand for a low-cost small-sized demodulator that is applicable to various fields of a proximity IC card, by eliminating the necessity of the conventional PLL circuit.
To achieve the foregoing objects, according to the present invention, there is provided a carrier synchronization type demodulator for a PSK signal, which receives and demodulates PSK-modulated subcarrier signals synchronized with and superposed onto a sent carrier signal. This demodulator comprises carrier detecting means for detecting the subcarrier signals successively received in a predetermined time, phase-change-point detecting means for detecting a phase change point of the subcarrier signal after the subcarrier signal is detected, and data reception control means for controlling the reception of data of a predetermined format by employing a moment, at which the phase change point is detected, as a synchronization start point for receiving data, and by using an internal clock (signal) that is synchronized with the sent carrier signal by using the moment as a starting point of synchronization.
An embodiment of this demodulator further comprises majority decision means for making a majority decision on a plurality of values respectively represented by sampled subcarrier signals, which provide logical values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d of data bits during data is received, and for deciding that the logical value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d of the majority of the data bits is set to be the logical value of each thereof.
The majority decision means of this embodiment may output reception error information in the case that the number of the data bits having the logical value xe2x80x9c0xe2x80x9d is equal to the number of the data bits having the logical value xe2x80x9c1xe2x80x9d when the majority decision is made. Alternatively, the majority decision means of this embodiment may determine a comparison ratio between the number of the data bits having the logical value xe2x80x9c0xe2x80x9d and the number of the data bits having the logical value xe2x80x9c1xe2x80x9d and output reception error information when the ratio is within a predetermined range.
Another embodiment of the demodulator further comprises determination means for determining, immediately upon completion of reception of a data frame of the predetermined format, whether not the reception of the next data frame has commenced. When the commencement of the reception of the next data frame is not detected, the phase-change-point detecting means immediately starts detecting a phase change point of the subcarrier signal.
In this embodiment, the data frame of the predetermined format is of the start-stop synchronization type (namely, the asynchronous type). Further, when the values of sampled subcarrier signals of the predetermined number immediately subsequent to a stop bit indicating the end of a data frame have the same logical value as that of the stop bit, the determination means determines that the commencement of the reception of the next data frame cannot be detected.